VHDL is hard mmkay.
I've spent a great deal of the last 2.5 days arguing with VHDL, which is a very powerful language for describing logic circuits. It allows you do define the behaviour of very complicated custom ICs, which is what is needed to pack most of a ZX Spectrum (or 3) into one chip.
The problem with VHDL, is that it is very easy to create something that looks right, but is in fact, wrong.
Missing a single state as it applies to an internal signal causes that signal to become a latch (meaning it retains its value, even when it's not supposed to). Not correctly defining your state conditions can lead to inadvertently setting a logic line to one value permanently, which in turn causes a whole pile of logic to disappear because the output of it is always the same.
The result of all this, is about 100 warnings about unused logic signals being removed, combinational loops being introduced (where the input of something is determined by its own output) and a whole pile of missing logic.
I have, however, now got it to the point where it synthesizes correctly. Now I can get back to adding in the remaining features, which are the overlay ROM logic (startup menu, "NMI" menu, etc), and system call traps (TAP loading, SAVEing [a call to error C]).
Then I can start assigning pins, design a dev board, and start doing the real work.
The problem with VHDL, is that it is very easy to create something that looks right, but is in fact, wrong.
Missing a single state as it applies to an internal signal causes that signal to become a latch (meaning it retains its value, even when it's not supposed to). Not correctly defining your state conditions can lead to inadvertently setting a logic line to one value permanently, which in turn causes a whole pile of logic to disappear because the output of it is always the same.
The result of all this, is about 100 warnings about unused logic signals being removed, combinational loops being introduced (where the input of something is determined by its own output) and a whole pile of missing logic.
I have, however, now got it to the point where it synthesizes correctly. Now I can get back to adding in the remaining features, which are the overlay ROM logic (startup menu, "NMI" menu, etc), and system call traps (TAP loading, SAVEing [a call to error C]).
Then I can start assigning pins, design a dev board, and start doing the real work.
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